Full and Half Subtractor

The Full Subtractor is a combinational circuit which is used to perform subtraction of three bits. It has three inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D (difference) and B (borrow).


The Half Subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).


Truth Table for Half Subtractor:

X	Y	D	B
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

Schematic Diagram for Half Subtractor:



Truth Table for Full Subtractor:

x	y	z	D	B
0	0	0	0	0
0	0	1	1	1
0	1	0	1	1
0	1	1	0	1
1	0	0	1	0
1	0	1	0	0
1	1	0	0	0
1	1	1	1	1

Schematic Diagram for Full Subtractor:

Full and Half Adder

A Full Adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and C_in; A and B are the operands, and C_in is a bit carried in from the next less significant stage. The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. 

The Half Adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + S. The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.

Truth Table for Full Adder:

Schematic Diagram:

Programmable Array Logic(PAL)

The term Programmable Array Logic (PAL) is used to describe a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in March 1978. MMI obtained a registered trademark on the term PAL for use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice Semiconductor.

PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.

Truth Table for PAL:

Schematic Diagram for PAL:

Programmable Logic Array(PLA)

A Programmable Logic Array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized in the sum of products (and sometimes product of sums) canonical forms.

Truth Table for PLA:

x2	x1	x0	z1	z0
0	0	0	0	0
0	0	1	1	0
0	1	0	0	0
0	1	1	1	0
1	0	0	1	1
1	0	1	0	0
1	1	0	0	0
1	1	1	0	1

Schematic Diagram for PLA:

Subtracting Binary Numbers

These are the steps in SUBTRACTING Binary Numbers:

• Just like in adding, you must first align the binary numbers accordingly.
• Apply the rules of subtracting in each column remember that (0-0=0, 1-0=1, 1-1=0, 0-1=1borrow 1)
• Repeat  the steps for other columns.

Examples of Subtracting Binary Numbers:

• 1011011 − 10010 = 1001001:

	1	0	1	1	0	1	1
−			1	0	0	1	0
	1	0	0	1	0	0	1

• 1010110 − 101010 = 101100:

	0		0
	×1	10	×1	10	1	1	0
−		1	0	1	0	1	0
		1	0	1	1	0	0

• 1000101 − 101100 = 11001:

	0	1	1
	×1	×10	×10	10	1	0	1
−		1	0	1	1	0	0
			1	1	0	0	1

• 100010110 − 1111010 = 10011100:

	0	1	1	1	10
	×1	×10	×10	×10	×1	10	1	1	0
−			1	1	1	1	0	1	0
		1	0	0	1	1	1	0	0

• 101101 − 100111 = 110:

			0	10
	1	0	×1	×1	10	1
−	1	0	0	1	1	1
				1	1	0

• 1110110 − 1010111 = 11111:

		0	10	1	10	10
	1	×1	×1	×10	×1	×1	10
−	1	0	1	0	1	1	1
			1	1	1	1	1

Adding Binary Numbers

Our topic is all about adding and subtracting binary numbers.

These are the steps in ADDING Binary Numbers:

• Align the binary numbers you wish to add.
• Add the binary numbers in each alignment.
• Apply the rules in adding binary numbers (ex. 0+0=0, 0+1=1, 1+1=0). With 1+1=0 there is a carry 1 then add it to the next column to the left.
• Repeat the steps for other columns. 

Examples of Adding Binary Numbers:

• 10001 + 11101 = 101110:

	1				1
		1	0	0	0	1
+		1	1	1	0	1
	1	0	1	1	1	0

• 101101 + 11001 = 1000110:

	1	1	1			1
		1	0	1	1	0	1
+			1	1	0	0	1
	1	0	0	0	1	1	0

• 1011001 + 111010 = 10010011:

	1	1	1	1
		1	0	1	1	0	0	1
+			1	1	1	0	1	0
	1	0	0	1	0	0	1	1

• 1110 + 1111 = 11101:

	1	1	1
		1	1	1	0
+		1	1	1	1
	1	1	1	0	1

• 10111 + 110101 = 1001100:

	1	1		1	1	1
			1	0	1	1	1
+		1	1	0	1	0	1
	1	0	0	1	1	0	0

• 11011 + 1001010 = 1100101:

		1	1		1
			1	1	0	1	1
+	1	0	0	1	0	1	0
	1	1	0	0	1	0	1